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1. general description the LPC2364/66/68 microcontrollers are based on a 16-bit/32-bit arm7tdmi-s cpu with real-time emulation that combines the microcontroller with up to 512 kb of embedded high-speed ?ash memory. a 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. for critical performance in interrupt service routines and dsp algorithms, this increases performance up to 30 % over thumb mode. for critical code size applications, the alternative 16-bit thumb mode reduces code by more than 30 % with minimal performance penalty. the LPC2364/66/68 are ideal for multi-purpose serial communication applications. they incorporate a 10/100 ethernet media access controller (mac), usb full speed device with 4 kb of endpoint ram, four uarts, two can channels, an spi interface, two synchronous serial ports (ssp), three i 2 c interfaces, and an i 2 s interface. this blend of serial communications interfaces combined with an on-chip 4 mhz internal oscillator, sram of up to 32 kb, 16 kb sram for ethernet, 8 kb sram for usb and general purpose use, together with 2 kb battery powered sram make these devices very well suited for communication gateways and protocol converters. various 32-bit timers, an improved 10-bit adc, 10-bit dac, one pwm unit, a can control unit, and up to 70 fast gpio lines with up to 12 edge or level sensitive external interrupt pins make these microcontrollers particularly suitable for industrial control and medical systems. 2. features n arm7tdmi-s processor, running at up to 72 mhz. n up to 512 kb on-chip ?ash program memory with in-system programming (isp) and in-application programming (iap) capabilities. flash program memory is on the arm local bus for high performance cpu access. n 8/32 kb of sram on the arm local bus for high performance cpu access. n 16 kb sram for ethernet interface. can also be used as general purpose sram. n 8 kb sram for general purpose dma use also accessible by the usb. n dual advanced high-performance bus (ahb) system that provides for simultaneous ethernet dma, usb dma, and program execution from on-chip ?ash with no contention between those functions. a bus bridge allows the ethernet dma to access the other ahb subsystem. n advanced vectored interrupt controller (vic), supporting up to 32 vectored interrupts. n general purpose ahb dma controller (gpdma) that can be used with the ssp serial interfaces, the i 2 s port, and the secure digital/multimediacard (sd/mmc) card port, as well as for memory-to-memory transfers. LPC2364/66/68 single-chip 16-bit/32-bit microcontrollers; up to 512 kb ?ash with isp/iap, ethernet, usb 2.0, can, and 10-bit adc/dac rev. 02 1 october 2007 preliminary data sheet
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 2 of 47 nxp semiconductors LPC2364/66/68 fast communication chip n serial interfaces: u ethernet mac with associated dma controller. these functions reside on an independent ahb bus. u usb 2.0 full-speed device with on-chip phy and associated dma controller. u four uarts with fractional baud rate generation, one with modem control i/o, one with irda support, all with fifo. u can controller with two channels. u spi controller. u two ssp controllers, with fifo and multi-protocol capabilities. one is an alternate for the spi port, sharing its interrupt and pins. these can be used with the gpdma controller. u three i 2 c-bus interfaces (one with open-drain and two with standard port pins). u i 2 s (inter-ic sound) interface for digital audio input or output. it can be used with the gpdma. n other peripherals: u sd/mmc memory card interface (lpc2368 only). u 70 general purpose i/o pins with con?gurable pull-up/down resistors. u 10-bit adc with input multiplexing among 6 pins. u 10-bit dac. u four general purpose timers/counters with a total of 8 capture inputs and 10 compare outputs. each timer block has an external count input. u one pwm/timer block with support for three-phase motor control. the pwm has two external count inputs. u real-time clock (rtc) with separate power pin, clock source can be the rtc oscillator or the apb clock. u 2 kb sram powered from the rtc power pin, allowing data to be stored when the rest of the chip is powered off. u watchdog timer (wdt). the wdt can be clocked from the internal rc oscillator, the rtc oscillator, or the apb clock. n standard arm test/debug interface for compatibility with existing tools. n emulation trace module supports real-time trace. n single 3.3 v power supply (3.0 v to 3.6 v). n four reduced power modes: idle, sleep, power-down, and deep power-down. n four external interrupt inputs con?gurable as edge/level sensitive. all pins on port0 and port2 can be used as edge sensitive interrupt sources. n processor wake-up from power-down mode via any interrupt able to operate during power-down mode (includes external interrupts, rtc interrupt, usb activity, ethernet wake-up interrupt). n two independent power domains allow ?ne tuning of power consumption based on needed features. n each peripheral has its own clock divider for further power saving. n brownout detect with separate thresholds for interrupt and forced reset. n on-chip power-on reset. n on-chip crystal oscillator with an operating range of 1 mhz to 24 mhz. n 4 mhz internal rc oscillator trimmed to 1 % accuracy that can optionally be used as the system clock. when used as the cpu clock, does not allow can and usb to run.
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 3 of 47 nxp semiconductors LPC2364/66/68 fast communication chip n on-chip pll allows cpu operation up to the maximum cpu rate without the need for a high frequency crystal. may be run from the main oscillator, the internal rc oscillator, or the rtc oscillator. n versatile pin function selections allow more possibilities for using on-chip peripheral functions. 3. applications n industrial control n medical systems n protocol converter n communications 4. ordering information 4.1 ordering options table 1. ordering information type number package name description version LPC2364fbd100 lqfp100 plastic low pro?le quad ?at package; 100 leads; body 14 14 1.4 mm sot407-1 lpc2366fbd100 lpc2368fbd100 table 2. ordering options type number flash (kb) sram (kb) ether net usb device +4kb fifo sd/ mmc gp dma channels temp range local bus ethernet buffers gp/ usb rtc total can adc dac LPC2364fbd100 128 8 16 8 2 34 rmii yes no yes 2 6 1 - 40 c to +85 c lpc2366fbd100 256 32 16 8 2 58 rmii yes no yes 2 6 1 - 40 c to +85 c lpc2368fbd100 512 32 16 8 2 58 rmii yes yes yes 2 6 1 - 40 c to +85 c
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 4 of 47 nxp semiconductors LPC2364/66/68 fast communication chip 5. block diagram (1) lpc2368 only. fig 1. LPC2364/66/68 block diagram pwm1 arm7tdmi-s pll eint3 to eint0 flash p3, p4 p0, p1, p2, legacy gpi/o 52 pins total p0, p1 sck, sck0 mosi, mosi0 ssel, ssel1 sck1 mosi1 mis01 ssel1 scl0, scl1, scl2 i2srx_clk i2stx_clk i2srx_ws i2stx_ws 6 ad0 rtcx1 rtcx2 mciclk, mcipwr rxd0, rxd2, rxd3 txd1 rxd1 rd1, rd2 td1, td2 can1, can2 usb_d+, usb_d - xtal1 tck tdo extin0 xtal2 reset trst tdi tms high-speed gpi/o 70 pins total LPC2364/66/68 8/32 kb sram 128/256/ 512 kb flash internal controllers test/debug interface emulation trace module trace signals ahb bridge ahb bridge ethernet mac with dma 16 kb sram master port ahb to apb bridge slave port system clock system functions internal rc oscillator v dda v dd(3v3) vref v ssa , v ss vectored interrupt controller 8 kb sram usb with 4 kb ram and dma gp dma controller i 2 s interface spi, ssp0 interface i2srx_sda i2stx_sda miso, miso0 ssp1 interface sd/mmc card interface (1) mcicmd, mcidat[3:0] txd0, txd2, txd3 uart0, uart2, uart3 uart1 dtr1, rts1 dsr1, cts1, dcd1, ri1 i 2 c0, i 2 c1, i 2 c2 sda0, sda1, sda2 external interrupts capture/compare timer0/timer1/ timer2/timer3 a/d converter d/a converter 2 kb battery ram rtc oscillator real- time clock watchdog timer system control 2 cap0/cap1/ cap2/cap3 4 mat2, 2 mat0/mat1/ mat3 6 pwm1 2 pcap1 aout vbat ahb to apb bridge sram rmii(8) v bus usb_connect usb_up_led 002aac566 p0, p2 power domain 2 ahb2 ahb1 power domain 2 v dd(dcdc)(3v3)
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 5 of 47 nxp semiconductors LPC2364/66/68 fast communication chip 6. pinning information 6.1 pinning 6.2 pin description fig 2. LPC2364/66/68 pinning LPC2364fbd100 lpc2366fbd100 lpc2368fbd100 75 26 50 100 76 51 1 25 002aac576 table 3. pin description symbol pin type description p0[0] to p0[31] i/o port 0: port 0 is a 32-bit i/o port with individual direction controls for each bit. the operation of port 0 pins depends upon the pin function selected via the pin connect block. pins 12, 13, 14, and 31 of this port are not available. p0[0]/rd1/txd3/ sda1 46 [1] i/o p0[0] general purpose digital input/output pin. i rd1 can1 receiver input. o txd3 transmitter output for uart3. i/o sda1 i 2 c1 data input/output (this is not an open-drain pin). p0[1]/td1/rxd3/ scl1 47 [1] i/o p0[1] general purpose digital input/output pin. o td1 can1 transmitter output. i rxd3 receiver input for uart3. i/o scl1 i 2 c1 clock input/output (this is not an open-drain pin). p0[2]/txd0 98 [1] i/o p0[2] general purpose digital input/output pin. o txd0 transmitter output for uart0. p0[3]/rxd0 99 [1] i/o p0[3] general purpose digital input/output pin. i rxd0 receiver input for uart0. p0[4]/ i2srx_clk/ rd2/cap2[0] 81 [1] i/o p0[4] general purpose digital input/output pin. i/o i2srx_clk receive clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus speci?cation . i rd2 can2 receiver input. i cap2[0] capture input for timer 2, channel 0.
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 6 of 47 nxp semiconductors LPC2364/66/68 fast communication chip p0[5]/ i2srx_ws/ td2/cap2[1] 80 [1] i/o p0[5] general purpose digital input/output pin. i/o i2srx_ws receive word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus speci?cation . o td2 can2 transmitter output. i cap2[1] capture input for timer 2, channel 1. p0[6]/ i2srx_sda/ ssel1/mat2[0] 79 [1] i/o p0[6] general purpose digital input/output pin. i/o i2srx_sda receive data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus speci?cation . i/o ssel1 slave select for ssp1. o mat2[0] match output for timer 2, channel 0. p0[7]/ i2stx_clk/ sck1/mat2[1] 78 [1] i/o p0[7] general purpose digital input/output pin. i/o i2stx_clk transmit clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus speci?cation . i/o sck1 serial clock for ssp1. o mat2[1] match output for timer 2, channel 1. p0[8]/ i2stx_ws/ miso1/mat2[2] 77 [1] i/o p0[8] general purpose digital input/output pin. i/o i2stx_ws transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus speci?cation . i/o miso1 master in slave out for ssp1. o mat2[2] match output for timer 2, channel 2. p0[9]/ i2stx_sda/ mosi1/mat2[3] 76 [1] i/o p0[9] general purpose digital input/output pin. i/o i2stx_sda transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus speci?cation . i/o mosi1 master out slave in for ssp1. o mat2[3] match output for timer 2, channel 3. p0[10]/txd2/ sda2/mat3[0] 48 [1] i/o p0[10] general purpose digital input/output pin. o txd2 transmitter output for uart2. i/o sda2 i 2 c2 data input/output (this is not an open-drain pin). o mat3[0] match output for timer 3, channel 0. p0[11]/rxd2/ scl2/mat3[1] 49 [1] i/o p0[11] general purpose digital input/output pin. i rxd2 receiver input for uart2. i/o scl2 i 2 c2 clock input/output (this is not an open-drain pin). o mat3[1] match output for timer 3, channel 1. p0[15]/txd1/ sck0/sck 62 [1] i/o p0[15] general purpose digital input/output pin. o txd1 transmitter output for uart1. i/o sck0 serial clock for ssp0. i/o sck serial clock for spi. p0[16]/rxd1/ ssel0/ssel 63 [1] i/o p0[16] general purpose digital input/output pin. i rxd1 receiver input for uart1. i/o ssel0 slave select for ssp0. i/o ssel slave select for spi. table 3. pin description continued symbol pin type description
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 7 of 47 nxp semiconductors LPC2364/66/68 fast communication chip p0[17]/cts1/ miso0/miso 61 [1] i/o p0[17] general purpose digital input/output pin. i cts1 clear to send input for uart1. i/o miso0 master in slave out for ss1 i/o miso master in slave out for spi. p0[18]/dcd1/ mosi0/mosi 60 [1] i/o p0[18] general purpose digital input/output pin. i dcd1 data carrier detect input for uart1. i/o mosi0 master out slave in for ssp0. i/o mosi master out slave in for spi. p0[19]/dsr1/ mciclk/sda1 59 [1] i/o p0[19] general purpose digital input/output pin. i dsr1 data set ready input for uart1. o mciclk clock output line for sd/mmc interface. (lpc2368 only) i/o sda1 i 2 c1 data input/output (this is not an open-drain pin). p0[20]/dtr1/ mcicmd/scl1 58 [1] i/o p0[20] general purpose digital input/output pin. o dtr1 data terminal ready output for uart1. i mcicmd command line for sd/mmc interface. (lpc2368 only) i/o scl1 i 2 c1 clock input/output (this is not an open-drain pin). p0[21]/ri1/ mcipwr/rd1 57 [1] i/o p0[21] general purpose digital input/output pin. i ri1 ring indicator input for uart1. o mcipwr power supply enable for external sd/mmc power supply. (lpc2368 only) i rd1 can1 receiver input. p0[22]/rts1/ mcidat0/td1 56 [1] i/o p0[22] general purpose digital input/output pin. o rts1 request to send output for uart1. o mcidat0 data line for sd/mmc interface. (lpc2368 only) o td1 can1 transmitter output. p0[23]/ad0[0]/ i2srx_clk/ cap3[0] 9 [2] i/o p0[23] general purpose digital input/output pin. i ad0[0] a/d converter 0, input 0. i/o i2srx_clk receive clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus speci?cation . i cap3[0] capture input for timer 3, channel 0. p0[24]/ad0[1]/ i2srx_ws/ cap3[1] 8 [2] i/o p0[24] general purpose digital input/output pin. i ad0[1] a/d converter 0, input 1. i/o i2srx_ws receive word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus speci?cation . i cap3[1] capture input for timer 3, channel 1. p0[25]/ad0[2]/ i2srx_sda/ txd3 7 [2] i/o p0[25] general purpose digital input/output pin. i ad0[2] a/d converter 0, input 2. i/o i2srx_sda receive data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus speci?cation . o txd3 transmitter output for uart3. table 3. pin description continued symbol pin type description
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 8 of 47 nxp semiconductors LPC2364/66/68 fast communication chip p0[26]/ad0[3]/ aout/rxd3 6 [3] i/o p0[26] general purpose digital input/output pin. i ad0[3] a/d converter 0, input 3. o aout d/a converter output. i rxd3 receiver input for uart3. p0[27]/sda0 25 [4] i/o p0[27] general purpose digital input/output pin. i/o sda0 i 2 c0 data input/output. open-drain output (for i 2 c-bus compliance). p0[28]/scl0 24 [4] i/o p0[28] general purpose digital input/output pin. i/o scl0 i 2 c0 clock input/output. open-drain output (for i 2 c-bus compliance). p0[29]/usb_d+ 29 [5] i/o p0[29] general purpose digital input/output pin. i/o usb_d+ usb bidirectional d+ line. p0[30]/usb_d - 30 [5] i/o p0[30] general purpose digital input/output pin. i/o usb_d - usb bidirectional d - line. p1[0] to p1[31] i/o port 1: port 1 is a 32-bit i/o port with individual direction controls for each bit. the operation of port 1 pins depends upon the pin function selected via the pin connect block. pins 2, 3, 5, 6, 7, 11, 12, and 13 of this port are not available. p1[0]/ enet_txd0 95 [1] i/o p1[0] general purpose digital input/output pin. o enet_txd0 ethernet transmit data 0. p1[1]/ enet_txd1 94 [1] i/o p1[1] general purpose digital input/output pin. o enet_txd1 ethernet transmit data 1. p1[4]/ enet_tx_en 93 [1] i/o p1[4] general purpose digital input/output pin. o enet_tx_en ethernet transmit data enable. p1[8]/ enet_crs 92 [1] i/o p1[8] general purpose digital input/output pin. i enet_crs ethernet carrier sense. p1[9]/ enet_rxd0 91 [1] i/o p1[9] general purpose digital input/output pin. i enet_rxd0 ethernet receive data. p1[10]/ enet_rxd1 90 [1] i/o p1[10] general purpose digital input/output pin. i enet_rxd1 ethernet receive data. p1[14]/ enet_rx_er 89 [1] i/o p1[14] general purpose digital input/output pin. i enet_rx_er ethernet receive error. p1[15]/ enet_ref_clk 88 [1] i/o p1[15] general purpose digital input/output pin. i enet_ref_clk/enet_rx_clk ethernet receiver clock. p1[16]/ enet_mdc 87 [1] i/o p1[16] general purpose digital input/output pin. i enet_mdc ethernet miim clock. p1[17]/ enet_mdio 86 [1] i/o p1[17] general purpose digital input/output pin. i/o enet_mdio ethernet mi data input and output. p1[18]/ usb_up_led/ pwm1[1]/ cap1[0] 32 [1] i/o p1[18] general purpose digital input/output pin. o usb_up_led usb goodlink led indicator. it is low when device is con?gured (non-control endpoints enabled). it is high when the device is not con?gured or during global suspend. o pwm1[1] pulse width modulator 1, channel 1 output. i cap1[0] capture input for timer 1, channel 0. table 3. pin description continued symbol pin type description
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 9 of 47 nxp semiconductors LPC2364/66/68 fast communication chip p1[19]/cap1[1] 33 [1] i/o p1[19] general purpose digital input/output pin. i cap1[1] capture input for timer 1, channel 1. p1[20]/pwm1[2]/ sck0 34 [1] i/o p1[20] general purpose digital input/output pin. o pwm1[2] pulse width modulator 1, channel 2 output. i/o sck0 serial clock for ssp0. p1[21]/pwm1[3]/ ssel0 35 [1] i/o p1[21] general purpose digital input/output pin. o pwm1[3] pulse width modulator 1, channel 3 output. i/o ssel0 slave select for ssp0. p1[22]/mat1[0] 36 [1] i/o p1[22] general purpose digital input/output pin. o mat1[0] match output for timer 1, channel 0. p1[23]/pwm1[4]/ miso0 37 [1] i/o p1[23] general purpose digital input/output pin. o pwm1[4] pulse width modulator 1, channel 4 output. i/o miso0 master in slave out for ssp0. p1[24]/pwm1[5]/ mosi0 38 [1] i/o p1[24] general purpose digital input/output pin. o pwm1[5] pulse width modulator 1, channel 5 output. i/o mosi0 master out slave in for ssp0. p1[25]/mat1[1] 39 [1] i/o p1[25] general purpose digital input/output pin. o mat1[1] match output for timer 1, channel 1. p1[26]/pwm1[6]/ cap0[0] 40 [1] i/o p1[26] general purpose digital input/output pin. o pwm1[6] pulse width modulator 1, channel 6 output. i cap0[0] capture input for timer 0, channel 0. p1[27]/cap0[1] 43 [1] i/o p1[27] general purpose digital input/output pin. i cap0[1] capture input for timer 0, channel 1. p1[28]/ pcap1[0]/ mat0[0] 44 [1] i/o p1[28] general purpose digital input/output pin. i pcap1[0] capture input for pwm1, channel 0. o mat0[0] match output for timer 0, channel 0. p1[29]/ pcap1[1]/ mat0[1] 45 [1] i/o p1[29] general purpose digital input/output pin. i pcap1[1] capture input for pwm1, channel 1. o mat0[1] match output for timer 0, channel 0. p1[30]/v bus / ad0[4] 21 [2] i/o p1[30] general purpose digital input/output pin. i v bus indicates the presence of usb bus power. note: this signal must be high for usb reset to occur. i ad0[4] a/d converter 0, input 4. p1[31]/sck1/ ad0[5] 20 [2] i/o p1[31] general purpose digital input/output pin. i/o sck1 serial clock for ssp1. i ad0[5] a/d converter 0, input 5. p2[0] to p2[31] i/o port 2: port 2 is a 32-bit i/o port with individual direction controls for each bit. the operation of port 2 pins depends upon the pin function selected via the pin connect block. pins 14 through 31 of this port are not available. table 3. pin description continued symbol pin type description
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 10 of 47 nxp semiconductors LPC2364/66/68 fast communication chip p2[0]/pwm1[1]/ txd1/ traceclk 75 [1] i/o p2[0] general purpose digital input/output pin. o pwm1[1] pulse width modulator 1, channel 1 output. o txd1 transmitter output for uart1. o traceclk trace clock. p2[1]/pwm1[2]/ rxd1/ pipestat0 74 [1] i/o p2[1] general purpose digital input/output pin. o pwm1[2] pulse width modulator 1, channel 2 output. i rxd1 receiver input for uart1. o pipestat0 pipeline status, bit 0. p2[2]/pwm1[3]/ cts1/ pipestat1 73 [1] i/o p2[2] general purpose digital input/output pin. o pwm1[3] pulse width modulator 1, channel 3 output. i cts1 clear to send input for uart1. o pipestat1 pipeline status, bit 1. p2[3]/pwm1[4]/ dcd1/ pipestat2 70 [1] i/o p2[3] general purpose digital input/output pin. o pwm1[4] pulse width modulator 1, channel 4 output. i dcd1 data carrier detect input for uart1. o pipestat2 pipeline status, bit 2. p2[4]/pwm1[5]/ dsr1/ tracesync 69 [1] i/o p2[4] general purpose digital input/output pin. o pwm1[5] pulse width modulator 1, channel 5 output. i dsr1 data set ready input for uart1. o tracesync trace synchronization. p2[5]/pwm1[6]/ dtr1/ tracepkt0 68 [1] i/o p2[5] general purpose digital input/output pin. o pwm1[6] pulse width modulator 1, channel 6 output. o dtr1 data terminal ready output for uart1. o tracepkt0 trace packet, bit 0. p2[6]/pcap1[0]/ ri1/ tracepkt1 67 [1] i/o p2[6] general purpose digital input/output pin. i pcap1[0] capture input for pwm1, channel 0. i ri1 ring indicator input for uart1. o tracepkt1 trace packet, bit 1. p2[7]/rd2/ rts1/ tracepkt2 66 [1] i/o p2[7] general purpose digital input/output pin. i rd2 can2 receiver input. o rts1 request to send output for uart1. o tracepkt2 trace packet, bit 2. p2[8]/td2/ txd2/ tracepkt3 65 [1] i/o p2[8] general purpose digital input/output pin. o td2 can2 transmitter output. o txd2 transmitter output for uart2. o tracepkt3 trace packet, bit 3. p2[9]/ usb_connect/ rxd2/ extin0 64 [1] i/o p2[9] general purpose digital input/output pin. o usb_connect signal used to switch an external 1.5 k w resistor under software control. used with the softconnect usb feature. i rxd2 receiver input for uart2. i extin0 external trigger input. table 3. pin description continued symbol pin type description
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 11 of 47 nxp semiconductors LPC2364/66/68 fast communication chip p2[10]/ eint0 53 [6] i/o p2[10] general purpose digital input/output pin. note: low on this pin while reset is low forces on-chip bootloader to take over control of the part after a reset. i eint0 external interrupt 0 input. p2[11]/ eint1/ mcidat1/ i2stx_clk 52 [6] i/o p2[11] general purpose digital input/output pin. i eint1 external interrupt 1 input. o mcidat1 data line for sd/mmc interface. (lpc2368 only) i/o i2stx_clk transmit clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus speci?cation . p2[12]/ eint2/ mcidat2/ i2stx_ws 51 [6] i/o p2[12] general purpose digital input/output pin. i eint2 external interrupt 2 input. o mcidat2 data line for sd/mmc interface. (lpc2368 only) i/o i2stx_ws transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus speci?cation . p2[13]/ eint3/ mcidat3/ i2stx_sda 50 [6] i/o p2[13] general purpose digital input/output pin. i eint3 external interrupt 3 input. o mcidat3 data line for sd/mmc interface. (lpc2368 only) i/o i2stx_sda transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus speci?cation . p3[0] to p3[31] i/o port 3: port 3 is a 32-bit i/o port with individual direction controls for each bit. the operation of port 3 pins depends upon the pin function selected via the pin connect block. pins 0 through 24, and 27 through 31 of this port are not available. p3[25]/mat0[0]/ pwm1[2] 27 [1] i/o p3[25] general purpose digital input/output pin. o mat0[0] match output for timer 0, channel 0. o pwm1[2] pulse width modulator 1, output 2. p3[26]/mat0[1]/ pwm1[3] 26 [1] i/o p3[26] general purpose digital input/output pin. o mat0[1] match output for timer 0, channel 1. o pwm1[3] pulse width modulator 1, output 3. p4[0] to p4[31] i/o port 4: port 4 is a 32-bit i/o port with individual direction controls for each bit. the operation of port 4 pins depends upon the pin function selected via the pin connect block. pins 0 through 27, 30, and 31 of this port are not available. p4[28]/mat2[0]/ txd3 82 [1] i/o p4[28] general purpose digital input/output pin. o mat2[0] match output for timer 2, channel 0. o txd3 transmitter output for uart3. p4[29]/mat2[1]/ rxd3 85 [1] i/o p4[29] general purpose digital input/output pin. o mat2[1] match output for timer 2, channel 1. i rxd3 receiver input for uart3. tdo 1 [1] o tdo test data out for jtag interface. tdi 2 [1] i tdi test data in for jtag interface. tms 3 [1] i tms test mode select for jtag interface. trst 4 [1] i trst test reset for jtag interface. tck 5 [1] i tck test clock for jtag interface. table 3. pin description continued symbol pin type description
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 12 of 47 nxp semiconductors LPC2364/66/68 fast communication chip [1] 5 v tolerant pad providing digital i/o functions with ttl levels and hysteresis. [2] 5 v tolerant pad providing digital i/o functions (with ttl levels and hysteresis) and analog input. when con?gured as a dac input, digital section of the pad is disabled. [3] 5 v tolerant pad providing digital i/o with ttl levels and hysteresis and analog output function. when con?gured as the dac o utput, digital section of the pad is disabled. [4] open-drain 5 v tolerant digital i/o i 2 c-bus 400 khz speci?cation compatible pad. it requires an external pull-up to provide output functionality. when power is switched off, this pin connected to the i 2 c-bus is ?oating and does not disturb the i 2 c lines. [5] pad provides digital i/o and usb functions. it is designed in accordance with the usb speci?cation, revision 2.0 (full-speed and low-speed mode only). [6] 5 v tolerant pad with 5 ns glitch ?lter providing digital i/o functions with ttl levels and hysteresis [7] 5 v tolerant pad with 20 ns glitch ?lter providing digital i/o function with ttl levels and hysteresis [8] pad provides special analog functionality. [9] pad provides special analog functionality. [10] pad provides special analog functionality. [11] pad provides special analog functionality. [12] pad provides special analog functionality. [13] pad provides special analog functionality. rtck 100 [1] i/o rtck jtag interface control signal. note: low on this pin while reset is low enables etm pins (p2[9:0]) to operate as trace port after reset. rst out 14 [1] o rst out this is a 1.8 v pin. low on this pin indicates LPC2364/66/68 being in reset state. reset 17 [7] i external reset input: a low on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. ttl with hysteresis, 5 v tolerant. xtal1 22 [8] i input to the oscillator circuit and internal clock generator circuits. xtal2 23 [8] o output from the oscillator ampli?er. rtcx1 16 [8] i input to the rtc oscillator circuit. rtcx2 18 [8] o output from the rtc oscillator circuit. v ss 15, 31, 41, 55, 72, 97, 83 [9] i ground: 0 v reference. v ssa 11 [10] i analog ground: 0 v reference. this should nominally be the same voltage as v ss , but should be isolated to minimize noise and error. v dd(3v3) 28, 54, 71, 96 [11] i 3.3 v supply voltage: this is the power supply voltage for the i/o ports. v dd(dcdc)(3v3) 13, 42, 84 [12] i 3.3 v dc-to-dc converter supply voltage: this is the supply voltage for the on-chip dc-to-dc converter only. v dda 10 [13] i analog 3.3 v pad supply voltage: this should be nominally the same voltage as v dd(3v3) but should be isolated to minimize noise and error. this voltage is used to power the adc and dac. vref 12 [13] i adc reference: this should be nominally the same voltage as v dd(3v3) but should be isolated to minimize noise and error. level on this pin is used as a reference for adc and dac. vbat 19 [13] i rtc power supply: 3.3 v on this pin supplies the power to the rtc. table 3. pin description continued symbol pin type description
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 13 of 47 nxp semiconductors LPC2364/66/68 fast communication chip 7. functional description 7.1 architectural overview the LPC2364/66/68 microcontroller consists of an arm7tdmi-s cpu with emulation support, the arm7 local bus for closely coupled, high-speed access to the majority of on-chip memory, the amba ahb interfacing to high-speed on-chip peripherals, and the amba apb for connection to other on-chip peripheral functions. the microcontroller permanently con?gures the arm7tdmi-s processor for little-endian byte order. the LPC2364/66/68 implements two ahb buses in order to allow the ethernet block to operate without interference caused by other system activity. the primary ahb, referred to as ahb1, includes the vic and gpdma controller. the second ahb, referred to as ahb2, includes only the ethernet block and an associated 16 kb sram. in addition, a bus bridge is provided that allows the secondary ahb to be a bus master on ahb1, allowing expansion of ethernet buffer space into off-chip memory or unused space in memory residing on ahb1. in summary, bus masters with access to ahb1 are the arm7 itself, the gpdma function, and the ethernet block (via the bus bridge from ahb2). bus masters with access to ahb2 are the arm7 and the ethernet block. ahb peripherals are allocated a 2 mb range of addresses at the very top of the 4 gb arm memory space. each ahb peripheral is allocated a 16 kb address space within the ahb address space. lower speed peripheral functions are connected to the apb bus. the ahb to apb bridge interfaces the apb bus to the ahb bus. apb peripherals are also allocated a 2 mb range of addresses, beginning at the 3.5 gb address point. each apb peripheral is allocated a 16 kb address space within the apb address space. the arm7tdmi-s processor is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. the arm architecture is based on reduced instruction set computer (risc) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed complex instruction set computers. this simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. the arm7tdmi-s processor also employs a unique architectural strategy known as thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. the key idea behind thumb is that of a super-reduced instruction set. essentially, the arm7tdmi-s processor has two instruction sets: ? the standard 32-bit arm set ? a 16-bit thumb set
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 14 of 47 nxp semiconductors LPC2364/66/68 fast communication chip the thumb sets 16-bit instruction length allows it to approach twice the density of standard arm code while retaining most of the arms performance advantage over a traditional 16-bit processor using 16-bit registers. this is possible because thumb code operates on the same 32-bit register set as arm code. thumb code is able to provide up to 65 % of the code size of arm, and 160 % of the performance of an equivalent arm processor connected to a 16-bit memory system. 7.2 on-chip ?ash programming memory the LPC2364/66/68 incorporate a 128 kb, 256 kb, and 512 kb ?ash memory system respectively. this memory may be used for both code and data storage. programming of the ?ash memory may be accomplished in several ways. it may be programmed in system via the serial port (uart0). the application program may also erase and/or program the ?ash while the application is running, allowing a great degree of ?exibility for data storage ?eld and ?rmware upgrades. the ?ash memory is 128 bits wide and includes pre-fetching and buffering techniques to allow it to operate at sram speeds of 72 mhz. the LPC2364/66/68 provides a minimum of 100000 write/erase cycles and 20 years of data retention. 7.3 on-chip sram the LPC2364/66/68 includes a sram memory of 8 kb, 32 kb, and 32 kb respectively, reserved for the arm processor exclusive use. this ram may be used for code and/or data storage and may be accessed as 8 bits, 16 bits, and 32 bits. a 16 kb sram block serving as a buffer for the ethernet controller and an 8 kb sram associated with the usb device can be used both for data and code storage, too. remaining sram such as a 4 kb usb fifo and a 2 kb rtc sram can be used for data storage only. the rtc sram is battery powered and retains the content in the absence of the main power supply. 7.4 memory map the LPC2364/66/68 memory map incorporates several distinct regions as shown in figure 3 . in addition, the cpu interrupt vectors may be remapped to allow them to reside in either ?ash memory (default), boot rom, or sram (see section 7.25.6 ).
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 15 of 47 nxp semiconductors LPC2364/66/68 fast communication chip 7.5 interrupt controller the arm processor core has two interrupt inputs called interrupt request (irq) and fast interrupt request (fiq). the vic takes 32 interrupt request inputs which can be programmed as fiq or vectored irq types. the programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. fig 3. LPC2364/66/68 memory map 0.0 gb 1.0 gb total of 128 kb on-chip non-volatile memory (LPC2364) total of 512 kb on-chip non-volatile memory (lpc2368) total of 256 kb on-chip non-volatile memory (lpc2366) 0x0000 0000 0x0001 ffff 0x0002 0000 0x0003 ffff 0x0007 ffff 0x0008 0000 0x0004 0000 reserved for on-chip memory 8 kb local on-chip static ram (LPC2364) 32 kb local on-chip static ram (lpc2366/lpc2368) reserved address space reserved address space 0x4000 0000 0x4000 2000 0x4000 8000 0x7fd0 0000 0x7fe0 0000 0x7fd0 1fff 0x7fe0 3fff 0x4000 1fff 0x4000 7fff 2.0 gb 0x8000 0000 boot rom and boot flash (boot flash remapped from on-chip flash) 3.0 gb 0xc000 0000 reserved address space 3.75 gb 4.0 gb 3.5 gb ahb peripherals apb peripherals 0xe000 0000 0xf000 0000 0xffff ffff usb ram (8 kb) ethernet ram (16 kb) 002aac577
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 16 of 47 nxp semiconductors LPC2364/66/68 fast communication chip fiqs have the highest priority. if more than one request is assigned to fiq, the vic ors the requests to produce the fiq signal to the arm processor. the fastest possible fiq latency is achieved when only one request is classi?ed as fiq, because then the fiq service routine can simply start dealing with that device. but if more than one request is assigned to the fiq class, the fiq service routine can read a word from the vic that identi?es which fiq source(s) is (are) requesting an interrupt. vectored irqs, which include all interrupt requests that are not classi?ed as fiqs, have a programmable interrupt priority. when more than one interrupt is assigned the same priority and occur simultaneously, the one connected to the lowest numbered vic channel will be serviced ?rst. the vic ors the requests from all of the vectored irqs to produce the irq signal to the arm processor. the irq service routine can start by reading a register from the vic and jumping to the address supplied by that register. 7.5.1 interrupt sources each peripheral device has one interrupt line connected to the vic but may have several interrupt ?ags. individual interrupt ?ags may also represent more than one interrupt source. any pin on port0 and port2 (total of 42 pins) regardless of the selected function, can be programmed to generate an interrupt on a rising edge, a falling edge, or both. such interrupt request coming from port0 and/or port2 will be combined with the eint3 interrupt requests. 7.6 pin connect block the pin connect block allows selected pins of the microcontroller to have more than one function. con?guration registers control the multiplexers to allow connection between the pin and the on chip peripherals. peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. activity of any enabled peripheral function that is not mapped to a related pin should be considered unde?ned. 7.7 general purpose dma controller the gpdma is an amba ahb compliant peripheral allowing selected LPC2364/66/68 peripherals to have dma support. the gpdma enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. each dma stream provides unidirectional serial dma transfers for a single source and destination. for example, a bidirectional port requires one stream for transmit and one for receive. the source and destination areas can each be either a memory region or a peripheral, and can be accessed through the ahb master. 7.7.1 features ? two dma channels. each channel can support a unidirectional transfer. ? the gpdma can transfer data between the 8 kb sram and peripherals such as the sd/mmc, two ssp, and i 2 s interfaces.
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 17 of 47 nxp semiconductors LPC2364/66/68 fast communication chip ? single dma and burst dma request signals. each peripheral connected to the gpdma can assert either a burst dma request or a single dma request. the dma burst size is set by programming the gpdma. ? memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers. ? scatter or gather dma is supported through the use of linked lists. this means that the source and destination areas do not have to occupy contiguous areas of memory. ? hardware dma channel priority. each dma channel has a speci?c hardware priority. dma channel 0 has the highest priority and channel 1 has the lowest priority. if requests from two channels become active at the same time the channel with the highest priority is serviced ?rst. ? ahb slave dma programming interface. the gpdma is programmed by writing to the dma control registers over the ahb slave interface. ? one ahb bus master for transferring data. this interface transfers data when a dma request goes active. ? 32-bit ahb master bus width. ? incrementing or non-incrementing addressing for source and destination. ? programmable dma burst size. the dma burst size can be programmed to more ef?ciently transfer data. usually the burst size is set to half the size of the fifo in the peripheral. ? internal four-word fifo per channel. ? supports 8-bit, 16-bit, and 32-bit wide transactions. ? an interrupt to the processor can be generated on a dma completion or when a dma error has occurred. ? interrupt masking. the dma error and dma terminal count interrupt requests can be masked. ? raw interrupt status. the dma error and dma count raw interrupt status can be read prior to masking. 7.8 fast general purpose parallel i/o device pins that are not connected to a speci?c peripheral function are controlled by the gpio registers. pins may be dynamically con?gured as inputs or outputs. separate registers allow setting or clearing any number of outputs simultaneously. the value of the output register may be read back as well as the current state of the port pins. LPC2364/66/68 use accelerated gpio functions: ? gpio registers are relocated to the arm local bus so that the fastest possible i/o timing can be achieved. ? mask registers allow treating sets of port bits as a group, leaving other bits unchanged. ? all gpio registers are byte and half-word addressable. ? entire port value can be written in one instruction.
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 18 of 47 nxp semiconductors LPC2364/66/68 fast communication chip additionally, any pin on port0 and port2 (total of 42 pins) providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. the edge detection is asynchronous, so it may operate when clocks are not present such as during power-down mode. each enabled interrupt can be used to wake up the chip from power-down mode. 7.8.1 features ? bit level set and clear registers allow a single instruction to set or clear any number of bits in one port. ? direction control of individual bits. ? all i/o default to inputs after reset. ? backward compatibility with other earlier devices is maintained with legacy port0 and port1 registers appearing at the original addresses on the apb bus. 7.9 ethernet the ethernet block contains a full featured 10 mbit/s or 100 mbit/s ethernet mac designed to provide optimized performance through the use of dma hardware acceleration. features include a generous suite of control registers, half or full duplex operation, ?ow control, control frames, hardware acceleration for transmit retry, receive packet ?ltering and wake-up on lan activity. automatic frame transmission and reception with scatter-gather dma off-loads many operations from the cpu. the ethernet block and the cpu share a dedicated ahb subsystem that is used to access the ethernet sram for ethernet data, control, and status information. all other ahb traf?c in the LPC2364/66/68 takes place on a different ahb subsystem, effectively separating ethernet activity from the rest of the system. the ethernet dma can also access the usb sram if it is not being used by the usb block. the ethernet block interfaces between an off-chip ethernet phy using the reduced mii (rmii) protocol and the on-chip media independent interface management (miim) serial bus. 7.9.1 features ? ethernet standards support: C supports 10 mbit/s or 100 mbit/s phy devices including 10 base-t, 100 base-tx, 100 base-fx, and 100 base-t4. C fully compliant with ieee standard 802.3. C fully compliant with 802.3x full duplex flow control and half duplex back pressure. C flexible transmit and receive frame options. C virtual local area network (vlan) frame support. ? memory management: C independent transmit and receive buffers memory mapped to shared sram. C dma managers with scatter/gather dma and arrays of frame descriptors. C memory traf?c optimized by buffering and pre-fetching.
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 19 of 47 nxp semiconductors LPC2364/66/68 fast communication chip ? enhanced ethernet features: C receive ?ltering. C multicast and broadcast frame support for both transmit and receive. C optional automatic frame check sequence (fcs) insertion with circular redundancy check (crc) for transmit. C selectable automatic transmit frame padding. C over-length frame support for both transmit and receive allows any length frames. C promiscuous receive mode. C automatic collision back-off and frame retransmission. C includes power management by clock switching. C wake-on-lan power management support allows system wake-up: using the receive ?lters or a magic frame detection ?lter. ? physical interface: C attachment of external phy chip through standard rmii interface. C phy register access is available via the miim interface. 7.10 usb interface the universal serial bus (usb) is a 4-wire bus that supports communication between a host and a number (127 maximum) of peripherals. the host controller allocates the usb bandwidth to attached devices through a token based protocol. the bus supports hot plugging, unplugging, and dynamic con?guration of the devices. all transactions are initiated by the host controller. 7.10.1 usb device controller the device controller enables 12 mbit/s data exchange with a usb host controller. it consists of register interface, serial interface engine, endpoint buffer memory, and the dma controller. the serial interface engine decodes the usb data stream and writes data to the appropriate end point buffer memory. the status of a completed usb transfer or error condition is indicated via status registers. an interrupt is also generated if enabled. the dma controller when enabled transfers data between the endpoint buffer and the usb ram. 7.10.2 features ? fully compliant with usb 2.0 speci?cation (full speed). ? supports 32 physical (16 logical) endpoints with a 4 kb usb buffer. ? supports control, bulk, interrupt and isochronous endpoints. ? scalable realization of endpoints at run time. ? endpoint maximum packet size selection (up to usb maximum speci?cation) by software at run time. ? supports softconnect and goodlink features. ? while usb is in the suspend mode, LPC2364/66/68 can enter one of the reduced power-down modes and wake up on a usb activity. ? supports dma transfers with the dma ram of 8 kb on all non-control endpoints.
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 20 of 47 nxp semiconductors LPC2364/66/68 fast communication chip ? allows dynamic switching between cpu-controlled and dma modes. ? double buffer implementation for bulk and isochronous endpoints. 7.11 can controller and acceptance ?lters the controller area network (can) is a serial communications protocol which ef?ciently supports distributed real-time control with a very high level of security. its domain of application ranges from high-speed networks to low cost multiplex wiring. the can block is intended to support multiple can buses simultaneously, allowing the device to be used as a gateway, switch, or router among a number of can buses in industrial or automotive applications. each can controller has a register structure similar to the nxp sja1000 and the pelican library block, but the 8-bit registers of those devices have been combined in 32-bit words to allow simultaneous access in the arm environment. the main operational difference is that the recognition of received identi?ers, known in can terminology as acceptance filtering, has been removed from the can controllers and centralized in a global acceptance filter. 7.11.1 features ? two can controllers and buses. ? data rates to 1 mbit/s on each bus. ? 32-bit register and ram access. ? compatible with can speci?cation 2.0b, iso 11898-1 . ? global acceptance filter recognizes 11-bit and 29-bit receive identi?ers for all can buses. ? acceptance filter can provide fullcan-style automatic reception for selected standard identi?ers. ? full can messages can generate interrupts. 7.12 10-bit adc the LPC2364/66/68 contain one adc. it is a single 10-bit successive approximation adc with six channels. 7.12.1 features ? 10-bit successive approximation adc. ? input multiplexing among 6 pins. ? power-down mode. ? measurement range 0 v to v i(vref) . ? 10-bit conversion time 3 2.44 m s. ? burst conversion mode for single or multiple inputs. ? optional conversion on transition of input pin or timer match signal. ? individual result registers for each adc channel to reduce interrupt overhead.
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 21 of 47 nxp semiconductors LPC2364/66/68 fast communication chip 7.13 10-bit dac the dac allows the LPC2364/66/68 to generate a variable analog output. the maximum output value of the dac is v i(vref) . 7.13.1 features ? 10-bit dac ? resistor string architecture ? buffered output ? power-down mode ? selectable output drive 7.14 uarts the LPC2364/66/68 each contain four uarts. in addition to standard transmit and receive data lines, uart1 also provides a full modem control handshake interface. the uarts include a fractional baud rate generator. standard baud rates such as 115200 can be achieved with any crystal frequency above 2 mhz. 7.14.1 features ? 16 b receive and transmit fifos. ? register locations conform to 16c550 industry standard. ? receiver fifo trigger points at 1 b, 4 b, 8 b, and 14 b. ? built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. ? fractional divider for baud rate control, auto baud capabilities and fifo control mechanism that enables software ?ow control implementation. ? uart1 equipped with standard modem interface signals. this module also provides full support for hardware ?ow control (auto-cts/rts). ? uart3 includes an irda mode to support infrared communication. 7.15 spi serial i/o controller the LPC2364/66/68 each contain one spi controller. spi is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. only a single master and a single slave can communicate on the interface during a given data transfer. during a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master. 7.15.1 features ? compliant with spi speci?cation ? synchronous, serial, full duplex communication ? combined spi master and slave ? maximum data bit rate of one eighth of the input clock rate ? 8 bits to 16 bits per transfer
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 22 of 47 nxp semiconductors LPC2364/66/68 fast communication chip 7.16 ssp serial i/o controller the LPC2364/66/68 each contain two ssp controllers. the ssp controller is capable of operation on a spi, 4-wire ssi, or microwire bus. it can interact with multiple masters and slaves on the bus. only a single master and a single slave can communicate on the bus during a given data transfer. the ssp supports full duplex transfers, with frames of 4 bits to 16 bits of data ?owing from the master to the slave and from the slave to the master. in practice, often only one of these data ?ows carries meaningful data. 7.16.1 features ? compatible with motorola spi, 4-wire ti ssi, and national semiconductor microwire buses ? synchronous serial communication ? master or slave operation ? 8-frame fifos for both transmit and receive ? 4-bit to 16-bit frame ? dma transfers supported by gpdma 7.17 sd/mmc card interface (lpc2368 only) the secure digital and multimedia card interface (mci) allows access to external sd memory cards. the sd card interface conforms to the sd multimedia card speci?cation version 2.11 . 7.17.1 features ? the mci interface provides all functions speci?c to the sd/mmc memory card. these include the clock generation unit, power management control, and command and data transfer. ? conforms to multimedia card speci?cation v2.11 . ? conforms to secure digital memory card physical layer speci?cation, v0.96. ? can be used as a multimedia card bus or a secure digital memory card bus host. the sd/mmc can be connected to several multimedia cards or a single secure digital memory card. ? dma supported through the gpdma controller. 7.18 i 2 c-bus serial i/o controllers the LPC2364/66/68 each contain three i 2 c-bus controllers. the i 2 c-bus is bidirectional, for inter-ic control using only two wires: a serial clock line (scl), and a serial data line (sda). each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an lcd driver) or a transmitter with the capability to both receive and send information (such as memory). transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c is a multi-master bus, it can be controlled by more than one bus master connected to it. the i 2 c-bus implemented in LPC2364/66/68 supports bit rates up to 400 kbit/s (fast i 2 c-bus).
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 23 of 47 nxp semiconductors LPC2364/66/68 fast communication chip 7.18.1 features ? i 2 c0 is a standard i 2 c compliant bus interface with open-drain pins. ? i 2 c1 and i 2 c2 use standard i/o pins and do not support powering off of individual devices connected to the same bus lines. ? easy to con?gure as master, slave, or master/slave. ? programmable clocks allow versatile rate control. ? bidirectional data transfer between masters and slaves. ? multi-master bus (no central master). ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? the i 2 c-bus can be used for test and diagnostic purposes. 7.19 i 2 s-bus serial i/o controllers the i 2 s-bus provides a standard communication interface for digital audio applications. the i 2 s-bus speci?cation de?nes a 3-wire serial bus using one data line, one clock line, and one word select signal. the basic i 2 s connection has one master, which is always the master, and one slave. the i 2 s interface on the LPC2364/66/68 provides a separate transmit and receive channel, each of which can operate as either a master or a slave. 7.19.1 features ? the interface has separate input/output channels each of which can operate in master or slave mode. ? capable of handling 8-bit, 16-bit, and 32-bit word sizes. ? mono and stereo audio data supported. ? the sampling frequency can range from 16 khz to 48 khz (16, 22.05, 32, 44.1, 48) khz. ? con?gurable word select period in master mode (separately for i 2 s input and output). ? two 8-word fifo data buffers are provided, one for transmit and one for receive. ? generates interrupt requests when buffer levels cross a programmable boundary. ? two dma requests, controlled by programmable buffer levels. these are connected to the gpdma block. ? controls include reset, stop and mute options separately for i 2 s input and i 2 s output.
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 24 of 47 nxp semiconductors LPC2364/66/68 fast communication chip 7.20 general purpose 32-bit timers/external event counters the LPC2364/66/68 include four 32-bit timer/counters. the timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. it can optionally generate interrupts or perform other actions at speci?ed timer values, based on four match registers. the timer/counter also includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.20.1 features ? a 32-bit timer/counter with a programmable 32-bit prescaler. ? counter or timer operation. ? two 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. a capture event may also generate an interrupt. ? four 32-bit match registers that allow: C continuous operation with optional interrupt generation on match. C stop timer on match with optional interrupt generation. C reset timer on match with optional interrupt generation. ? up to four external outputs corresponding to match registers, with the following capabilities: C set low on match. C set high on match. C toggle on match. C do nothing on match. 7.21 pulse width modulator the pwm is based on the standard timer block and inherits all of its features, although only the pwm function is pinned out on the LPC2364/66/68. the timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when speci?ed timer values occur, based on seven match registers. the pwm function is in addition to these features, and is based on match register events. the ability to separately control rising and falling edge locations allows the pwm to be used for more applications. for instance, multi-phase motor control typically requires three non-overlapping pwm outputs with individual control of all three pulse widths and positions. two match registers can be used to provide a single edge controlled pwm output. one match register (pwmmr0) controls the pwm cycle rate, by resetting the count upon match. the other match register controls the pwm edge position. additional single edge controlled pwm outputs require only one match register each, since the repetition rate is the same for all pwm outputs. multiple single edge controlled pwm outputs will all have a rising edge at the beginning of each pwm cycle, when an pwmmr0 match occurs. three match registers can be used to provide a pwm output with both edges controlled. again, the pwmmr0 match register controls the pwm cycle rate. the other match registers control the two pwm edge positions. additional double edge controlled pwm outputs require only two match registers each, since the repetition rate is the same for all pwm outputs.
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 25 of 47 nxp semiconductors LPC2364/66/68 fast communication chip with double edge controlled pwm outputs, speci?c match registers control the rising and falling edge of the output. this allows both positive going pwm pulses (when the rising edge occurs prior to the falling edge), and negative going pwm pulses (when the falling edge occurs prior to the rising edge). 7.21.1 features ? LPC2364/66/68 has one pwm block with counter or timer operation (may use the peripheral clock or one of the capture inputs as the clock source). ? seven match registers allow up to 6 single edge controlled or 3 double edge controlled pwm outputs, or a mix of both types. the match registers also allow: C continuous operation with optional interrupt generation on match. C stop timer on match with optional interrupt generation. C reset timer on match with optional interrupt generation. ? supports single edge controlled and/or double edge controlled pwm outputs. single edge controlled pwm outputs all go high at the beginning of each cycle unless the output is a constant low. double edge controlled pwm outputs can have either edge occur at any position within a cycle. this allows for both positive going and negative going pulses. ? pulse period and width can be any number of timer counts. this allows complete ?exibility in the trade-off between resolution and repetition rate. all pwm outputs will occur at the same repetition rate. ? double edge controlled pwm outputs can be programmed to be either positive going or negative going pulses. ? match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. software must release new match values before they can become effective. ? may be used as a standard timer if the pwm mode is not enabled. ? a 32-bit timer/counter with a programmable 32-bit prescaler. 7.22 watchdog timer the purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. when enabled, the watchdog will generate a system reset if the user program fails to feed (or reload) the watchdog within a predetermined amount of time. 7.22.1 features ? internally resets chip if not periodically reloaded. ? debug mode. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. ? incorrect/incomplete feed sequence causes reset/interrupt if enabled. ? flag to indicate watchdog reset. ? programmable 32-bit timer with internal prescaler.
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 26 of 47 nxp semiconductors LPC2364/66/68 fast communication chip ? selectable time period from (t cy(wdclk) 256 4) to (t cy(wdclk) 2 32 4) in multiples of t cy(wdclk) 4. ? the watchdog clock (wdclk) source can be selected from the rtc clock, the internal rc oscillator (irc), or the apb peripheral clock. this gives a wide range of potential timing choices of watchdog operation under different power reduction conditions. it also provides the ability to run the wdt from an entirely internal source that is not dependent on an external crystal and its associated components and wiring, for increased reliability. 7.23 rtc and battery ram the rtc is a set of counters for measuring time when system power is on, and optionally when it is off. it uses little power in power-down mode. on the LPC2364/66/68, the rtc can be clocked by a separate 32.768 khz oscillator, or by a programmable prescale divider based on the apb clock. also, the rtc is powered by its own power supply pin, vbat, which can be connected to a battery or to the same 3.3 v supply used by the rest of the device. the vbat pin supplies power only to the rtc and the battery ram. these two functions require a minimum of power to operate, which can be supplied by an external battery. 7.23.1 features ? measures the passage of time to maintain a calendar and clock. ? ultra low power design to support battery powered systems. ? provides seconds, minutes, hours, day of month, month, year, day of week, and day of year. ? dedicated 32 khz oscillator or programmable prescaler from apb clock. ? dedicated power supply pin can be connected to a battery or to the main 3.3 v. ? periodic interrupts can be generated from increments of any ?eld of the time registers, and selected fractional second values. ? 2 kb data sram powered by vbat. ? rtc and battery ram power supply is isolated from the rest of the chip. 7.24 clocking and power control 7.24.1 crystal oscillators the LPC2364/66/68 includes three independent oscillators. these are the main oscillator, the internal rc oscillator, and the rtc oscillator. each oscillator can be used for more than one purpose as required in a particular application. any of the three clock sources can be chosen by software to drive the pll and ultimately the cpu. following reset, the LPC2364/66/68 will operate from the internal rc oscillator until switched by software. this allows systems to operate without any external crystal and the bootloader code to operate at a known frequency.
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 27 of 47 nxp semiconductors LPC2364/66/68 fast communication chip 7.24.1.1 internal rc oscillator the irc may be used as the clock source for the wdt, and/or as the clock that drives the pll and subsequently the cpu. the nominal irc frequency is 4 mhz. the irc is trimmed to 1 % accuracy. upon power-up or any chip reset, the LPC2364/66/68 uses the irc as the clock source. software may later switch to one of the other available clock sources. 7.24.1.2 main oscillator the main oscillator can be used as the clock source for the cpu, with or without using the pll. the main oscillator operates at frequencies of 1 mhz to 24 mhz. this frequency can be boosted to a higher frequency, up to the maximum cpu operating frequency, by the pll. the clock selected as the pll input is pllclkin. the arm processor clock frequency is referred to as cclk elsewhere in this document. the frequencies of pllclkin and cclk are the same value unless the pll is active and connected. the clock frequency for each peripheral can be selected individually and is referred to as pclk. refer to section 7.24.2 for additional information. 7.24.1.3 rtc oscillator the rtc oscillator can be used as the clock source for the rtc and/or the wdt. also, the rtc oscillator can be used to drive the pll and the cpu. 7.24.2 pll the pll accepts an input clock frequency in the range of 32 khz to 50 mhz. the input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the cpu and the usb block. the pll input, in the range of 32 khz to 50 mhz, may initially be divided down by a value n, which may be in the range of 1 to 256. this input division provides a wide range of output frequencies from the same input frequency. following the pll input divider is the pll multiplier. this can multiply the input divider output through the use of a current controlled oscillator (cco) by a value m, in the range of 1 through 32768. the resulting frequency must be in the range of 275 mhz to 550 mhz. the multiplier works by dividing the cco output by the value of m, then using a phase-frequency detector to compare the divided cco output to the multiplier input. the error value is used to adjust the cco frequency. the pll is turned off and bypassed following a chip reset and by entering power-down mode. pll is enabled by software only. the program must con?gure and activate the pll, wait for the pll to lock, then connect to the pll as a clock source. 7.24.3 wake-up timer the LPC2364/66/68 begins operation at power-up and when awakened from power-down mode or deep power-down mode by using the 4 mhz irc oscillator as the clock source. this allows chip operation to resume quickly. if the main oscillator or the pll is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source.
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 28 of 47 nxp semiconductors LPC2364/66/68 fast communication chip when the main oscillator is initially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. this is important at power on, all types of reset, and whenever any of the aforementioned functions are turned off for any reason. since the oscillator and other functions are turned off during power-down mode, any wake-up of the processor from power-down mode makes use of the wake-up timer. the wake-up timer monitors the crystal oscillator to check whether it is safe to begin code execution. when power is applied to the chip, or when some event caused the chip to exit power-down mode, some time is required for the oscillator to produce a signal of suf?cient amplitude to drive the clock logic. the amount of time depends on many factors, including the rate of v dd(3v3) ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. 7.24.4 power control the LPC2364/66/68 supports a variety of power control features. there are four special modes of processor power reduction: idle mode, sleep mode, power-down mode, and deep power-down mode. the cpu clock rate may also be controlled as needed by changing clock sources, recon?guring pll values, and/or altering the cpu clock divider value. this allows a trade-off of power versus processing speed based on application requirements. in addition, peripheral power control allows shutting down the clocks to individual on-chip peripherals, allowing ?ne tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. each of the peripherals has its own clock divider which provides even better power control. the LPC2364/66/68 also implements a separate power domain in order to allow turning off power to the bulk of the device while maintaining operation of the rtc and a small sram, referred to as the battery ram. 7.24.4.1 idle mode in idle mode, execution of instructions is suspended until either a reset or interrupt occurs. peripheral functions continue operation during idle mode and may generate interrupts to cause the processor to resume execution. idle mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 7.24.4.2 sleep mode in sleep mode, the oscillator is shut down and the chip receives no internal clocks. the processor state and registers, peripheral registers, and internal sram values are preserved throughout sleep mode and the logic levels of chip pins remain static. the output of the irc is disabled but the irc is not powered down for a fast wake-up later. the 32 khz rtc oscillator is not stopped because the rtc interrupts may be used as the wake-up source. the pll is automatically turned off and disconnected. the cclk and usb clock dividers automatically get reset to zero. the sleep mode can be terminated and normal operation resumed by either a reset or certain speci?c interrupts that are able to function without clocks. since all dynamic operation of the chip is suspended, sleep mode reduces chip power consumption to a very low value. the ?ash memory is left on in sleep mode, allowing a very quick wake-up.
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 29 of 47 nxp semiconductors LPC2364/66/68 fast communication chip on the wake-up of sleep mode, if the irc was used before entering sleep mode, the code execution and peripherals activities will resume after 4 cycles expire. if the main external oscillator was used, the code execution will resume when 4096 cycles expire. the customers need to recon?gure the pll and clock dividers accordingly. 7.24.4.3 power-down mode power-down mode does everything that sleep mode does, but also turns off the irc oscillator and the ?ash memory. this saves more power, but requires waiting for resumption of ?ash operation before execution of code or data access in the ?ash memory can be accomplished. on the wake-up of power-down mode, if the irc was used before entering power-down mode, it will take irc 60 m s to start-up. after this 4 irc cycles will expire before the code execution can then be resumed if the code was running from sram. in the meantime, the ?ash wake-up timer then counts 4 mhz irc clock cycles to make the 100 m s ?ash start-up time. when it times out, access to the ?ash will be allowed. the customers need to recon?gure the pll and clock dividers accordingly. 7.24.4.4 deep power-down mode deep power-down mode is like power-down mode, but the on-chip regulator that supplies power to internal logic is also shut off. this produces the lowest possible power consumption without actually removing power from the entire chip. since deep power-down mode shuts down the on-chip logic power supply, there is no register or memory retention, and resumption of operation involves the same activities as a full-chip reset. if power is supplied to the LPC2364/66/68 during deep power-down mode, wake-up can be caused by external reset. while in deep power-down mode, external device power may be removed. in this case, the LPC2364/66/68 will start up when external power is restored. essential data may be retained through deep power-down mode (or through complete powering off of the chip) by storing data in the battery ram, as long as the external power to the vbat pin is maintained. 7.24.4.5 power domains the LPC2364/66/68 provides two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the rtc and the battery ram. the 3.3 v (v dd(3v3) ) pins power both the on-chip dc-to-dc converter and the i/o pads. these pins provide the power for the cpu and most of the peripherals. if power is removed from the v dd(3v3) pins, the cpu and related peripherals stop. the vbat pin supplies power only to the rtc and the battery ram. these two functions require a minimum of power to operate, which can be supplied by an external battery.
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 30 of 47 nxp semiconductors LPC2364/66/68 fast communication chip 7.25 system control 7.25.1 reset reset has four sources on the LPC2364/66/68: the reset pin, the watchdog reset, power-on reset, and the brownout detection (bod) circuit. the reset pin is a schmitt trigger input pin. assertion of chip reset by any source, once the operating voltage attains a usable level, starts the wake-up timer (see description in section 7.24.3 w ak e-up timer ), causing reset to remain asserted until the external reset is de-asserted, the oscillator is running, a ?xed number of clocks have passed, and the ?ash controller has completed its initialization. when the internal reset is removed, the processor begins executing at address 0, which is initially the reset vector mapped from the boot block. at that point, all of the processor and peripheral registers have been initialized to predetermined values. 7.25.2 brownout detection the LPC2364/66/68 includes 2-stage monitoring of the voltage on the v dd(3v3) pins. if this voltage falls below 2.95 v, the bod asserts an interrupt signal to the vectored interrupt controller. this signal can be enabled for interrupt in the interrupt enable register in the vic in order to cause a cpu interrupt; if not, software can monitor the signal by reading a dedicated status register. the second stage of low-voltage detection asserts reset to inactivate the LPC2364/66/68 when the voltage on the v dd(3v3) pins falls below 2.65 v. this reset prevents alteration of the ?ash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. the bod circuit maintains this reset down below 1 v, at which point the power-on reset circuitry maintains the overall reset. both the 2.95 v and 2.65 v thresholds include some hysteresis. in normal operation, this hysteresis allows the 2.95 v detection to reliably interrupt, or a regularly executed event loop to sense the condition. 7.25.3 code security this feature of the LPC2364/66/68 allows an application to control whether it can be debugged or protected from observation. if after reset the on-chip bootloader detects a valid checksum in ?ash and reads 0x8765 4321 from address 0x1fc in ?ash, debugging will be disabled and thus the code in ?ash will be protected from observation. once debugging is disabled, it can be enabled by performing a full chip erase using the isp. 7.25.4 ahb bus the LPC2364/66/68 implements two ahb buses in order to allow the ethernet block to operate without interference caused by other system activity. the primary ahb, referred to as ahb1, includes the vectored interrupt controller, gpdma controller, usb interface, and 8 kb sram primarily intended for use by the usb. the second ahb, referred to as ahb2, includes only the ethernet block and an associated 16 kb sram. in addition, a bus bridge is provided that allows the secondary ahb to be a bus master on ahb1, allowing expansion of ethernet buffer space into unused space in memory residing on ahb1.
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 31 of 47 nxp semiconductors LPC2364/66/68 fast communication chip in summary, bus masters with access to ahb1 are the arm7 itself, the usb block, the gpdma function, and the ethernet block (via the bus bridge from ahb2). bus masters with access to ahb2 are the arm7 and the ethernet block. 7.25.5 external interrupt inputs the LPC2364/66/68 include up to 46 edge sensitive interrupt inputs combined with up to to four level sensitive external interrupt inputs as selectable pin functions. the external interrupt inputs can optionally be used to wake up the processor from power-down mode. 7.25.6 memory mapping control the memory mapping control alters the mapping of the interrupt vectors that appear at the beginning at address 0x0000 0000. vectors may be mapped to the bottom of the boot rom or the sram. this allows code running in different memory spaces to have control of the interrupts. 7.26 emulation and debugging the LPC2364/66/68 support emulation and debugging via a jtag serial port. a trace port allows tracing program execution. debugging and trace functions are multiplexed only with gpios on p2[0] to p2[9]. this means that all communication, timer, and interface peripherals residing on other pins are available during the development and debugging phase as they are when the application is run in the embedded system itself. 7.26.1 embeddedice the embeddedice logic provides on-chip debug support. the debugging of the target system requires a host computer running the debugger software and an embeddedice protocol convertor. the embeddedice protocol convertor converts the remote debug protocol commands to the jtag data needed to access the arm7tdmi-s core present on the target system. the arm core has a debug communication channel (dcc) function built-in. the dcc allows a program running on the target to communicate with the host debugger or another separate host without stopping the program ?ow or even entering the debug state. the dcc is accessed as a co-processor 14 by the program running on the arm7tdmi-s core. the dcc allows the jtag port to be used for sending and receiving data without affecting the normal program ?ow. the dcc data and control registers are mapped in to addresses in the embeddedice logic. 7.26.2 embedded trace since the LPC2364/66/68 have signi?cant amounts of on-chip memories, it is not possible to determine how the processor core is operating simply by observing the external pins. the etm provides real-time trace capability for deeply embedded processor cores. it outputs information about processor execution to a trace port. a software debugger allows con?guration of the etm using a jtag interface and displays the trace information that has been captured. the etm is connected directly to the arm core and not to the main amba system bus. it compresses the trace information and exports it through a narrow trace port. an external trace port analyzer captures the trace information under software debugger control. the trace port can broadcast the instruction trace information. instruction trace (or pc trace) shows the ?ow of execution of the processor and provides a list of all the instructions that
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 32 of 47 nxp semiconductors LPC2364/66/68 fast communication chip were executed. instruction trace is signi?cantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. trace information generation can be controlled by selecting the trigger resource. trigger resources include address comparators, counters and sequencers. since trace information is compressed the software debugger requires a static image of the code being executed. self-modifying code can not be traced because of this restriction. 7.26.3 realmonitor realmonitor is a con?gurable software module, developed by arm inc., which enables real-time debug. it is a lightweight debug monitor that runs in the background while users debug their foreground application. it communicates with the host using the dcc, which is present in the embeddedice logic. the LPC2364/66/68 contain a speci?c con?guration of realmonitor software programmed into the on-chip rom memory.
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 33 of 47 nxp semiconductors LPC2364/66/68 fast communication chip 8. limiting values [1] the following applies to the limiting values: a) this product includes circuitry speci?cally designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) parameters are valid over operating temperature range unless otherwise speci?ed. all voltages are with respect to v ss unless otherwise noted. [2] including voltage on outputs in 3-state mode. [3] not to exceed 4.6 v. [4] the peak current is limited to 25 times the corresponding maximum current. [5] dependent on package type. [6] human body model: equivalent to discharging a 100 pf capacitor through a 1.5 k w series resistor. table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd(3v3) supply voltage (3.3 v) core and external rail 3.0 3.6 v v dd(dcdc)(3v3) dc-to-dc converter supply voltage (3.3 v) 3.0 3.6 v v dda analog 3.3 v pad supply voltage - 0.5 +4.6 v v i(vbat) input voltage on pin vbat for the rtc - 0.5 +4.6 v v i(vref) input voltage on pin vref - 0.5 +4.6 v v ia analog input voltage on adc related pins - 0.5 +5.1 v v i input voltage 5 v tolerant i/o pins; only valid when the v dd(3v3) supply voltage is present [2] - 0.5 +6.0 v other i/o pins [2] [3] - 0.5 v dd(3v3) + 0.5 v i dd supply current per supply pin [4] - 100 ma i ss ground current per ground pin [4] - 100 ma t stg storage temperature [5] - 40 +125 c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 w v esd electrostatic discharge voltage human body model; all pins [6] - 2000 +2000 v
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 34 of 47 nxp semiconductors LPC2364/66/68 fast communication chip 9. static characteristics table 5. static characteristics t amb = - 40 c to +85 c for commercial applications, unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit v dd(3v3) supply voltage (3.3 v) core and external rail 3.0 3.3 3.6 v v dd(dcdc)(3v3) dc-to-dc converter supply voltage (3.3 v) 3.0 3.3 3.6 v v dda analog 3.3 v pad supply voltage 3.0 3.3 3.6 v v i(vbat) input voltage on pin vbat [2] 2.0 3.3 3.6 v v i(vref) input voltage on pin vref 2.5 3.3 v dda v standard port pins, reset, rtck i il low-level input current v i = 0 v; no pull-up - - 3 m a i ih high-level input current v i =v dd(3v3) ; no pull-down --3 m a i oz off-state output current v o =0v; v o =v dd(3v3) ; no pull-up/down --3 m a i latch i/o latch-up current - (0.5v dd(3v3) ) < v i < (1.5v dd(3v3) ); t j < 125 c - - 100 ma v i input voltage pin con?gured to provide a digital function [3] [4] [5] 0 - 5.5 v v o output voltage output active 0 - v dd(3v3) v v ih high-level input voltage 2.0 - - v v il low-level input voltage - - 0.8 v v hys hysteresis voltage - 0.4 - v v oh high-level output voltage i oh = - 4 ma [6] v dd(3v3) - 0.4 --v v ol low-level output voltage i ol = - 4 ma [6] - - 0.4 v i oh high-level output current v oh =v dd(3v3) - 0.4 v [6] - 4--ma i ol low-level output current v ol = 0.4 v [6] 4--ma i ohs high-level short-circuit output current v oh =0v [7] -- - 45 ma i ols low-level short-circuit output current v ol =v dda [7] - - 50 ma i pd pull-down current v i =5v [8] 10 50 150 m a i pu pull-up current v i =0v - 15 - 50 - 85 m a v dd(3v3) LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 35 of 47 nxp semiconductors LPC2364/66/68 fast communication chip i dd(dcdc)act(3v3) active mode dc-to-dc converter supply current (3.3 v) v dd(dcdc)(3v3) = 3.3 v; t amb =25 c; code while(1){} executed from ?ash; no peripherals enabled; pclk = cclk cclk = 10 mhz - 15 - ma cclk = 72 mhz - 63 - ma all peripherals enabled; pclk = cclk / 8 cclk = 10 mhz - 21 - ma cclk = 72 mhz - 92 - ma all peripherals enabled; pclk = cclk cclk = 10 mhz - 27 - ma cclk = 72 mhz - 125 - ma i dd(dcdc)pd(3v3) power-down mode dc-to-dc converter supply current (3.3 v) v dd(dcdc)(3v3) = 3.3 v; t amb =25 c - 150 - m a i dd(dcdc)dpd(3v3) deep power-down mode dc-to-dc converter supply current (3.3 v) v dd(dcdc)(3v3) = 3.3 v; t amb =25 c -15- m a i batact active mode battery supply current dc-to-dc converter on [9] -20- m a dc-to-dc converter off [9] -28- m a i 2 c-bus pins (p0[27] and p0[28]) v ih high-level input voltage 0.7v dd(3v3) --v v il low-level input voltage - - 0.3v dd(3v3) v v hys hysteresis voltage - 0.5v dd(3v3) -v v ol low-level output voltage i ols = 3 ma [6] - - 0.4 v i li input leakage current v i =v dd(3v3) [10] -24 m a v i =5v - 10 22 m a oscillator pins v i(xtal1) input voltage on pin xtal1 0 - 1.8 v v o(xtal2) output voltage on pin xtal2 0 - 1.8 v v i(rtcx1) input voltage on pin rtcx1 0 - 1.8 v v o(rtcx2) output voltage on pin rtcx2 0 - 1.8 v table 5. static characteristics continued t amb = - 40 c to +85 c for commercial applications, unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 36 of 47 nxp semiconductors LPC2364/66/68 fast communication chip [1] typical ratings are not guaranteed. the values listed are at room temperature (25 c), nominal supply voltages. [2] the rtc typically fails when v i(vbat) drops below 1.6 v. [3] including voltage on outputs in 3-state mode. [4] v dd(3v3) supply voltages must be present. [5] 3-state outputs go into 3-state mode when v dd(3v3) is grounded. [6] accounts for 100 mv voltage drop in all supply lines. [7] only allowed for a short time period. [8] minimum condition for v i = 4.5 v, maximum condition for v i = 5.5 v. [9] on pin v bat . [10] to v ss . [11] includes external resistors of 18 w 1 % on d+ and d - . usb pins i oz off-state output current 0v LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 37 of 47 nxp semiconductors LPC2364/66/68 fast communication chip [1] conditions: v ssa =0v, v dda = 3.3 v. [2] the adc is monotonic, there are no missing codes. [3] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 4 . [4] the integral non-linearity (e l(adj) ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 4 . [5] the offset error (e o ) is the absolute difference between the straight line which ?ts the actual curve and the straight line which ?ts the ideal curve. see figure 4 . [6] the gain error (e g ) is the relative difference in percent between the straight line ?tting the actual transfer curve after removing offset error, and the straight line which ?ts the ideal transfer curve. see figure 4 . [7] the absolute error (e t ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. see figure 4 . [8] see figure 5 . e g gain error [1] [6] -- 0.5 % e t absolute error [1] [7] -- 4 lsb r vsi voltage source interface resistance [8] --40k w table 6. adc static characteristics continued v dda = 2.5 v to 3.6 v; t amb = - 40 c to +85 c unless otherwise speci?ed; adc frequency 4.5 mhz. symbol parameter conditions min typ max unit
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 38 of 47 nxp semiconductors LPC2364/66/68 fast communication chip (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 4. adc characteristics 002aac046 1023 1022 1021 1020 1019 (2) (1) 1024 1018 1019 1020 1021 1022 1023 7 123456 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 lsb (ideal) code out v dda - v ssa 1024 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 39 of 47 nxp semiconductors LPC2364/66/68 fast communication chip fig 5. suggested adc interface - LPC2364/66/68 ad0[y] pin LPC2364/66/68 adx[y] sample adx[y] 20 k w 3 pf 5 pf r vsi v ss v ext 002aac575
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 40 of 47 nxp semiconductors LPC2364/66/68 fast communication chip 10. dynamic characteristics [1] characterized but not implemented as production test. guaranteed by design. [1] parameters are valid over operating temperature range unless otherwise speci?ed. [2] typical ratings are not guaranteed. the values listed are at room temperature (25 c), nominal supply voltages. [3] bus capacitance c b in pf, from 10 pf to 400 pf. table 7. dynamic characteristics of usb pins (full-speed) c l = 50 pf; r pu = 1.5 k w on d+ to v dd(3v3) , unless otherwise speci?ed. symbol parameter conditions min typ max unit t r rise time 10 % to 90 % 8.5 - 13.8 ns t f fall time 10 % to 90 % 7.7 - 13.7 ns t frfm differential rise and fall time matching t r /t f - - 109 % v crs output signal crossover voltage 1.3 - 2.0 v t feopt source se0 interval of eop see figure 7 160 - 175 ns t fdeop source jitter for differential transition to se0 transition see figure 7 - 2 - +5 ns t jr1 receiver jitter to next transition - 18.5 - +18.5 ns t jr2 receiver jitter for paired transitions 10 % to 90 % - 9 - +9 ns t eopr1 eop width at receiver must reject as eop; see figure 7 [1] 40 --ns t eopr2 eop width at receiver must accept as eop; see figure 7 [1] 82 --ns table 8. dynamic characteristics t amb = - 40 c to +85 c for commercial applications; v dd(3v3) over speci?ed ranges. [1] symbol parameter conditions min typ [2] max unit external clock f osc oscillator frequency 10 - 25 mhz t cy(clk) clock cycle time 40 - 100 ns t chcx clock high time t cy(clk) 0.4 - - ns t clcx clock low time t cy(clk) 0.4 - - ns t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns i 2 c-bus pins (p0[27] and p0[28]) t f(o) output fall time v ih to v il 20 + 0.1 c b [3] --ns
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 41 of 47 nxp semiconductors LPC2364/66/68 fast communication chip 10.1 timing fig 6. external clock timing t chcl t clcx t chcx t cy(clk) t clch 002aaa907 0.2v dd + 0.9 v 0.2v dd - 0.1 v v dd - 0.5 v 0.45 v fig 7. differential data-to-eop transition skew and eop width 002aab561 t period differential data lines crossover point source eop width: t feopt receiver eop width: t eopr1 , t eopr2 crossover point extended differential data to seo/eop skew n t period + t fdeop
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 42 of 47 nxp semiconductors LPC2364/66/68 fast communication chip 11. application information 11.1 suggested usb interface solutions fig 8. LPC2364/66/68 usb interface on a self-powered device lpc23xx usb-b connector usb_d+ usb_connect soft-connect switch usb_d - v bus v ss v dd(3v3) r1 1.5 k w r s = 33 w 002aac578 r s = 33 w usb_up_led fig 9. LPC2364/66/68 usb interface on a bus-powered device lpc23xx v dd(3v3) r1 1.5 k w r2 usb_up_led 002aac579 usb-b connector usb_d+ usb_d - v bus v ss r s = 33 w r s = 33 w
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 43 of 47 nxp semiconductors LPC2364/66/68 fast communication chip 12. package outline fig 10. package outline sot407-1 (lqfp100) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.25 15.75 1.15 0.85 7 0 o o 0.08 0.08 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot407-1 136e20 ms-026 00-02-01 03-02-20 d (1) (1) (1) 14.1 13.9 h d 16.25 15.75 e z 1.15 0.85 d b p e q e a 1 a l p detail x l (a ) 3 b 25 c d h b p e h a 2 v m b d z d a z e e v m a x 1 100 76 75 51 50 26 y pin 1 index w m w m 0 5 10 mm scale lqfp100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm sot407-1
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 44 of 47 nxp semiconductors LPC2364/66/68 fast communication chip 13. abbreviations table 9. abbreviations acronym description adc analog-to-digital converter ahb advanced high-performance bus amba advanced microcontroller bus architecture apb advanced peripheral bus bod brownout detection can controller area network dac digital-to-analog converter dcc debug communication channel dma direct memory access dsp digital signal processing eop end of packet etm embedded trace macrocell gpio general purpose input/output jtag joint test action group mii media independent interface phy physical layer pll phase-locked loop pwm pulse width modulator rmii reduced media independent interface se0 single ended zero spi serial peripheral interface ssi serial synchronous interface ssp synchronous serial port ttl transistor-transistor logic uart universal asynchronous receiver/transmitter usb universal serial bus
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 45 of 47 nxp semiconductors LPC2364/66/68 fast communication chip 14. revision history table 10. revision history document id release date data sheet status change notice supersedes LPC2364_66_68_2 20071001 preliminary data sheet - LPC2364_66_68_1 modi?cations: ? figure 1 , 7 , 8 and 9 : changed incorrect character font LPC2364_66_68_1 20070103 preliminary data sheet - -
LPC2364_66_68_2 ? nxp b.v. 2007. all rights reserved. preliminary data sheet rev. 02 1 october 2007 46 of 47 nxp semiconductors LPC2364/66/68 fast communication chip 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 15.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 15.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. softconnect is a trademark of nxp b.v. goodlink is a trademark of nxp b.v. 16. contact information for additional information, please visit: http://www .nxp.com for sales of?ce addresses, send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors LPC2364/66/68 fast communication chip ? nxp b.v. 2007. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 1 october 2007 document identifier: LPC2364_66_68_2 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 functional description . . . . . . . . . . . . . . . . . . 13 7.1 architectural overview. . . . . . . . . . . . . . . . . . . 13 7.2 on-chip ?ash programming memory . . . . . . . 14 7.3 on-chip sram . . . . . . . . . . . . . . . . . . . . . . . . 14 7.4 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.5 interrupt controller . . . . . . . . . . . . . . . . . . . . . 15 7.5.1 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 16 7.6 pin connect block . . . . . . . . . . . . . . . . . . . . . . 16 7.7 general purpose dma controller . . . . . . . . . . 16 7.7.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.8 fast general purpose parallel i/o . . . . . . . . . . 17 7.8.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.9 ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.10 usb interface . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.10.1 usb device controller . . . . . . . . . . . . . . . . . . . 19 7.10.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.11 can controller and acceptance ?lters . . . . . . 20 7.11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.12 10-bit adc . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.13 10-bit dac . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.14 uarts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.15 spi serial i/o controller. . . . . . . . . . . . . . . . . . 21 7.15.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.16 ssp serial i/o controller . . . . . . . . . . . . . . . . . 22 7.16.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.17 sd/mmc card interface (lpc2368 only) . . . . 22 7.17.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.18 i 2 c-bus serial i/o controllers. . . . . . . . . . . . . . 22 7.18.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.19 i 2 s-bus serial i/o controllers . . . . . . . . . . . . . . 23 7.19.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.20 general purpose 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . 24 7.20.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.21 pulse width modulator . . . . . . . . . . . . . . . . . . 24 7.21.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.22 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 25 7.22.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.23 rtc and battery ram . . . . . . . . . . . . . . . . . . 26 7.23.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.24 clocking and power control . . . . . . . . . . . . . . 26 7.24.1 crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 26 7.24.1.1 internal rc oscillator . . . . . . . . . . . . . . . . . . . 27 7.24.1.2 main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 27 7.24.1.3 rtc oscillator. . . . . . . . . . . . . . . . . . . . . . . . . 27 7.24.2 pll. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.24.3 wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 27 7.24.4 power control . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.24.4.1 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.24.4.2 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.24.4.3 power-down mode . . . . . . . . . . . . . . . . . . . . . 29 7.24.4.4 deep power-down mode . . . . . . . . . . . . . . . . 29 7.24.4.5 power domains. . . . . . . . . . . . . . . . . . . . . . . . 29 7.25 system control . . . . . . . . . . . . . . . . . . . . . . . . 30 7.25.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.25.2 brownout detection . . . . . . . . . . . . . . . . . . . . 30 7.25.3 code security . . . . . . . . . . . . . . . . . . . . . . . . 30 7.25.4 ahb bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.25.5 external interrupt inputs . . . . . . . . . . . . . . . . . 31 7.25.6 memory mapping control . . . . . . . . . . . . . . . . 31 7.26 emulation and debugging. . . . . . . . . . . . . . . . 31 7.26.1 embeddedice . . . . . . . . . . . . . . . . . . . . . . . . 31 7.26.2 embedded trace. . . . . . . . . . . . . . . . . . . . . . . 31 7.26.3 realmonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 33 9 static characteristics . . . . . . . . . . . . . . . . . . . 34 10 dynamic characteristics . . . . . . . . . . . . . . . . . 40 10.1 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11 application information . . . . . . . . . . . . . . . . . 42 11.1 suggested usb interface solutions . . . . . . . . 42 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 43 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 44 14 revision history . . . . . . . . . . . . . . . . . . . . . . . 45 15 legal information . . . . . . . . . . . . . . . . . . . . . . 46 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 46 15.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 15.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 46 15.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 46 16 contact information . . . . . . . . . . . . . . . . . . . . 46 17 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

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